UPD78F1502AGK-GAK-AX Datasheet, PDF (997/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(25/39)
Page
Serial
interface
If other I²C
If I²C operation is enabled and the device participates in communication already in p.616 _†
communications progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I²C
IICA
are already in recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
progress
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I²C communications. To avoid this, start I²C in the following
sequence.
<1> Clear bit 4 (SPIE) of IICCTL0 to 0 to disable generation of an interrupt request
signal (INTIICA) when the stop condition is detected.
<2> Set bit 7 (IICE) of IICCTL0 to 1 to enable the operation of I²C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL) of IICCTL0 to 1 before ACK is returned (4 to 80 clocks after
setting IICE to 1), to forcibly disable detection.
STT, SPT: Bits Setting STT and SPT (bits 1 and 0 of IICCTL0) again after they are set and before p.616 _†
1, 0 of IICA
they are cleared to 0 is prohibited.
control register 0
(IICCTL0)
Reserving
When transmission is reserved, set SPIE (bit 4 of IICTL0) to 1 so that an interrupt p.616 _†
transmission
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IICA after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE to 1 when MSTS (bit 7 of IICS) is
detected by software.
LCD
LCDMD: LCD Bits 0 to 3, 6 and 7 must be set to 0.
p.667 _†
controller/d mode register
river
LCDM: LCD
When LCD display is not performed or necessary, set SCOC and VLCON to 0, in p.668 _†
display mode order to reduce power consumption.
register
When the external resistance division method has been set (MDSET1 = MDSET0 = p.668 _†
0), do not set VLCON to 1.
Set BLON and LCDSEL to 0 when 8 has been selected as the number of time slices p.668 _†
for the display mode.
To use the internal voltage boosting method, specify the reference voltage by using p.668 _†
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
R01UH0004EJ0501 Rev.5.01
981
Jun 20, 2011