UPD78F1502AGK-GAK-AX Datasheet, PDF (397/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.1 Functions of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller is mounted onto all 78K0R/Lx3 microcontroller products.
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Figure 9-1 shows the block diagram of clock output/buzzer output controller.
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
PCLOE1 0
Internal bus
Clock output select register 1 (CKS1)
0
0 CSEL1 CCS12 CCS11 CCS10
fMAIN
fSUB
Prescaler
5
3 _fMAIN/211 _{to fMAIN/2}13
fMAIN to fMAIN/2⁴
fSUB to fSUB/2⁷
fMAIN/2¹¹ to fMAIN/2¹³
fMAIN to fMAIN/2⁴
88
Prescaler
fSUB to fSUB/2⁷
PCLOE1
Clock/buzzer
controller
Output latch
(P31)
PCLBUZ1^Note/P31/
TI00/TO03/RTCDIV/
RTCCL/INTP2
PM31
Clock/buzzer
controller
PCLBUZ0^Note/P32/
TI01/TO01/INTP5
PCLOE0
Output latch
(P32)
PM32
PCLOE0 0
0
0 CSEL0 CCS02 CCS01 CCS00
Clock output select register 0 (CKS0)
Internal bus
Note The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ VDD. Setting a clock
exceeding 5 MHz at VDD < 2.7 V is prohibited.
R01UH0004EJ0501 Rev.5.01
381
Jun 20, 2011