UPD78F1502AGK-GAK-AX Datasheet, PDF (622/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.9 Address match detection method
In I²C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
Address match can be detected automatically by hardware. An interrupt request (INTIICA) occurs when the address
set to the slave address register (SVA) matches the slave address sent by the master device, or when an extension code
has been received.
15.5.10 Error detection
In I²C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by the IICA shift register
(IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to
enable detection of transmission errors. A transmission error is judged as having occurred when the compared data
values do not match.
15.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC)
is set to 1 for extension code reception and an interrupt request (INTIICA) is issued at the falling edge of the eighth
clock. The local address stored in the slave address register (SVA) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when
the SVA register is set to 11110xx0. Note that INTIICA occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC = 1
• Seven bits of data match:
COI = 1
Remark EXC: Bit 5 of IICA status register (IICS)
COI: Bit 4 of IICA status register (IICS)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL) of the IICA control register 0 (IICCTL0) to 1 to set the standby mode for the next communication
operation.
Table 15-3. Bit Definitions of Main Extension Code
Slave Address
0000 000
1111 0xx
1111 0xx
R/W Bit
0
0
1
Description
General call address
10-bit slave address specification (for address authentication)
10-bit slave address specification (for read command issuance
after address match)
Remark For extension codes other than the above, refer to THE I²C-BUS SPECIFICATION published by NXP.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011