UPD78F1502AGK-GAK-AX Datasheet, PDF (614/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5 I²C Bus Definitions and Control Methods
The following section describes the I²C bus’s serial data communication format and the signals used by the I²C bus.
Figure 15-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I²C
bus’s serial data bus.
Figure 15-14. I²C Bus Serial Data Transfer Timing
SCL0
1-7
89
1-8
9
1-8
9
SDA0
Start
Address R/W ACK
condition
Data ACK
Data
ACK Stop
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
level period can be extended and a wait can be inserted.
15.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The
start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when
starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 15-15. Start Conditions
H
SCL0
SDA0
A start condition is output when bit 1 (STT) of IICA control register 0 (IICCTL0) is set (1) after a stop condition has been
detected (SPD: Bit 0 of the IICA status register (IICS) = 1). When a start condition is detected, bit 1 (STD) of IICS is set
(1).
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011