UPD78F1502AGK-GAK-AX Datasheet, PDF (606/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-7. Format of IICA Status Register (IICS) (2/3)
COI
Detection of matching addresses
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COI = 0)
Condition for setting (COI = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When the received address matches the local
address (slave address register (SVA))
(set at the rising edge of the eighth clock).
TRC
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRC = 0)
Condition for setting (TRC = 1)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
stop)
• Cleared by WREL = 1^Note (wait cancel)
• When the ALD bit changes from 0 to 1 (arbitration
loss)
• Reset
• When not used for communication (MSTS, EXC, COI = 0)
<Master>
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
(during address transfer)
<Slave>
• When 1 (slave transmission) is input to the LSB
(transfer direction specification bit) of the first byte
from the master (during address transfer)
Note When bit 3 (TRC) of the IICA status register (IICS) is set to 1 (transmission status), bit 5 (WREL) of
IICA control register 0 (IICCTL0) is set to 1 during the ninth clock and wait is canceled, after which
the TRC bit is cleared (reception status) and the SDA0 line is set to high impedance. Release the
wait performed while the TRC bit is 1 (transmission status) by writing to the IICA shift register.
Remark LREL: Bit 6 of IICA control register 0 (IICCTL0)
IICE: Bit 7 of IICA control register 0 (IICCTL0)
R01UH0004EJ0501 Rev.5.01
590
Jun 20, 2011