UPD78F1502AGK-GAK-AX Datasheet, PDF (620/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.7 Canceling wait
The I²C usually cancels a wait state by the following processing.
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)^Note
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)^Note
Note Master only
When the above wait canceling processing is executed, the I²C cancels the wait state and communication is resumed.
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of IICA control register
0 (IICCTL0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT) of IICCTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of IICCTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IICA.
In addition to the above, communication is stopped if IICE is cleared to 0 when communication has been aborted, so
that the wait state can be canceled.
If the I²C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of IICCTL0,
so that the wait state can be canceled.
Caution If a processing to cancel a wait state executed when WUP (bit 7 of IICA control register 1 (IICCTL1)) =
1, the wait state will not be canceled.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011