UPD78F1502AGK-GAK-AX Datasheet, PDF (641/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.17 Timing of I²C interrupt request (INTIICA) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICA, and the value of the IICS
register when the INTIICA signal is generated are shown below.
Remark
ST:
Start condition
AD6 to AD0: Address
R/W:
Transfer direction specification
ACK:
Acknowledge
D7 to D0: Data
SP:
Stop condition
R01UH0004EJ0501 Rev.5.01
625
Jun 20, 2011