UPD78F1502AGK-GAK-AX Datasheet, PDF (815/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
23.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 23-1.
Figure 23-1. Block Diagram of Power-on-Clear Circuit
VDD
VDD
+
Internal reset signal
−
Reference
voltage
source
23.3 Operation of Power-on-Clear Circuit
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection
voltage (VPDR = 1.61 V ±0.09 V), the reset status is released.
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
• The supply voltage (VDD) and detection voltage (VPDR = 1.59 V ±0.09 V) are compared. When VDD < VPDR, the
internal reset signal is generated.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown
below.
R01UH0004EJ0501 Rev.5.01
799
Jun 20, 2011