UPD78F1502AGK-GAK-AX Datasheet, PDF (257/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/6)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(A) → (B)
Status Transition
SFR Register Setting
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(A) → (B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(A) → (B) → (C)
(external main clock)
CMC Register ^{Note 1}
EXCLK
0
OSCSEL
1
AMPH
0
0
1
1
1
1
×
CSC
Register
MSTOP
0
0
0
OSMC
Register
FSEL
0
1^{Note 2}
0/1^{Note 2}
OSTC
Register
Must be
checked
Must be
checked
Must
not be
checked
CKC
Register
MCM0
1
1
1
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release.
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
CMC Register^Note
Status Transition
(A) → (B) → (D)
OSCSELS AMPHS1
1
0/1
AMPHS0
0/1
CSC
Register
XTSTOP
0
Waiting for
Oscillation
Stabilization
Necessary
CKC
Register
CSS
1
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Jun 20, 2011