UPD78F1502AGK-GAK-AX Datasheet, PDF (228/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Cautions 2. To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
3. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
OSC register.
4. The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting
Clock
Condition Before Stopping Clock
(Invalidating External Clock Input)
X1 clock
External main system
clock
CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.
• CLS = 0 and MCS = 0
• CLS = 1
Subsystem clock
CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.
(CLS = 0)
Internal high-speed
oscillation clock
CPU and peripheral hardware clocks operate with a clock
other than the internal high-speed oscillator clock and 20
MHz internal high-speed oscillation clock.
• CLS = 0 and MCS = 1
• CLS = 1
Setting of CSC
Register Flags
MSTOP = 1
XTSTOP = 1
HIOSTOP = 1
(3) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being used
as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of CSC register) = 1 clear OSTC to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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Jun 20, 2011