UPD78F1502AGK-GAK-AX Datasheet, PDF (581/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 14-98. Timing Chart of Stop Condition Generation
Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
R01UH0004EJ0501 Rev.5.01
565
Jun 20, 2011