UPD78F1502AGK-GAK-AX Datasheet, PDF (609/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(5) IICA control register 1 (IICCTL1)
This register is used to set the operation mode of I²C and detect the statuses of the SCL0 and SDA0 pins.
IICCTL1 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD and DAD bits are read-
only.
Set the IICCTL1 register, except the WUP bit, while operation of I²C is disabled (bit 7 (IICE) of IICA control register
0 (IICCTL0) is 0).
Reset signal generation clears this register to 00H.
Figure 15-9. Format of IICA Control Register 1 (IICCTL1) (1/2)
Address: F0231H
After reset: 00H
R/W^{Note 1}
Symbol
7
6
<5>
<4>
<3>
<2>
1
0
IICCTL1 WUP
0
CLD
DAD
SMC
DFC
0
0
WUP
Control of address match wakeup
0
Stops operation of address match wakeup function in STOP mode.
1
Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) the
WUP bit (see Figure 15-22 Flow When Setting WUP = 1).
Clear (0) the WUP bit after the address has matched or an extension code has been received. The subsequent
communication can be entered by the clearing (0) WUP bit. (The wait must be released and transmit data must
be written after the WUP bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE bit is set to 1.
When WUP = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master
device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a
start condition by setting (1) the STT bit, without waiting for the detection of the subsequent start condition or
stop condition.
Condition for clearing (WUP = 0)
Condition for setting (WUP = 1)
• Cleared by instruction (after address match or
extension code reception)
• Set by instruction (when the MSTS, EXC, and COI
bits are “0”, and the STD bit also “0” (communication
not entered))^{Note 2}
Notes 1. Bits 4 and 5 are read-only.
2. The status of the IICA status register (IICS) must be checked and the WUP bit must be set
during the period shown below.
<1>
<2>
SCL0
SDA0
A6 A5 A4 A3 A2 A1 A0 R/W
The maximum time from reading IICS to setting
WUP is the period from <1> to <2>.
Check the IICS operation status and set
WUP during this period.
R01UH0004EJ0501 Rev.5.01
593
Jun 20, 2011