UPD78F1502AGK-GAK-AX Datasheet, PDF (162/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 4 PORT FUNCTIONS
4.2.6 Port 5
<R>
P50/RxD3/SEGxx
P51/TxD3/SEGxx
P52/TI02/SEGxx
P53/TI04/SEGxx
P54/SEGxx
P55/SEGxx
P56/SEGxx
P57/SEGxx
78K0R/LF3
(80 pins: μ PD78F15x0A,
78F1501A, 78F15x2A)
√ (xx = 30)
√ (xx = 29)
√ (xx = 28)
√ (xx = 27)
√ (xx = 26)
√ (xx = 25)
√ (xx = 24)
√ (xx = 23)
78K0R/LG3
(100 pins: μ PD78F15x3A,
78F1504A, 78F15x5A)
√ (xx = 39)
√ (xx = 38)
√ (xx = 37)
√ (xx = 36)
√ (xx = 35)
√ (xx = 34)
√ (xx = 33)
√ (xx = 32)
78K0R/LH3
(128 pins: μ PD78F15x6A,
78F1507A, 78F15x8A)
√ (xx = 53)
√ (xx = 52)
√ (xx = 51)
√ (xx = 50)
√ (xx = 49)
√ (xx = 48)
√ (xx = 47)
√ (xx = 46)
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for serial interface data I/O, timer input and segment output of LCD controller/driver.
Reset signal generation sets port 5 to input mode.
Figures 4-12 to 4-14 show block diagrams of port 5.
R01UH0004EJ0501 Rev.5.01
146
Jun 20, 2011