UPD78F1502AGK-GAK-AX Datasheet, PDF (311/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Caution When TOEpq = 1, even if the output by timer interrupt of each timer (INTTMpq) contends with
writing to TOpq, output is normally done to TOpq pin.
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
6.4.5 Timer Interrupt and TOpq Pin Output at Operation Start
In the interval timer mode or capture mode, the MDmn0 bit in the TMRmn register sets whether or not to generate a
timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOpq output is controlled.
Figures 6-34 and 6-35 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 6-34. When MDmn0 is set to 1
TCRmn
TEmn
INTTMmn
TOpq
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOpq performs a toggle
operation.
Figure 6-35. When MDmn0 is set to 0
TCRmn
TEmn
INTTMmn
TOpq
Count operation start
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOpq does not change
either. After counting one cycle, INTTMmn is output and TOpq performs a toggle operation.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011