UPD78F1502AGK-GAK-AX Datasheet, PDF (475/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(9) Serial channel start register m (SSm)
SSm is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1. Because SSmn is a trigger bit, it is cleared immediately when SEmn = 1.
SSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SSm can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears this register to 0000H.
Figure 14-12. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0), F0162H, F0163H (SS1) After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
SSm
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
0 SSm SSm SSm SSm
3
2
1
0
SSmn
Operation start trigger of channel n
0 No trigger operation
1 Sets SEmn to 1 and enters the communication wait status (if a communication operation is already under
execution, the operation is stopped and the start condition is awaited).
Caution Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SSm register is read, 0000H is always read.
R01UH0004EJ0501 Rev.5.01
459
Jun 20, 2011