UPD78F1502AGK-GAK-AX Datasheet, PDF (800/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop the
watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and then
execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal
high-speed oscillation clock before the next execution of the STOP instruction. Before changing the
CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1
oscillation) after the STOP mode is released, check the oscillation stabilization time with the
oscillation stabilization time counter status register (OSTC).
4. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal high-speed
oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-speed
oscillation clock operation.
(2) STOP mode release
Figure 21-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request
Is Generated)
STOP mode release
STOP mode
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Wait for oscillation accuracy stabilization
HALT status
(oscillation stabilization time set by OSTS)^Note
High-speed system clock
Clock switched by software
High-speed system clock
Wait (2 clocks)
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
Internal high-speed
oscillation clock
High-speed system clock
Wait (1 clock)
Clock switched by software
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
Note When the oscillation stabilization time set by OSTS is equal to or shorter than 61 μs, the HALT status is
retained to a maximum of "61μs + wait time."
The STOP mode can be released by the following two sources.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011