UPD78F1502AGK-GAK-AX Datasheet, PDF (737/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
18.3 Registers Controlling DMA Controller
DMA controller is controlled by the following registers.
• DMA mode control register n (DMCn)
• DMA operation control register n (DRCn)
Remark n: DMA channel number (n = 0, 1)
(1) DMA mode control register n (DMCn)
DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction,
data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
DMCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 18-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
DMCn
STGn
DRSn
DSn
DWAITn
3
IFCn3
2
IFCn2
1
IFCn1
0
IFCn0
STGn^{Note 1}
DMA transfer start software trigger
0
No trigger operation
1
DMA transfer is started when DMA operation is enabled (DENn = 1).
DMA transfer is started by writing 1 to STGn when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DRSn
0
1
SFR to internal RAM
Internal RAM to SFR
Selection of DMA transfer direction
DSn
0
8 bits
1
16 bits
Specification of transfer data size for DMA transfer
DWAITn^{Note 2}
Pending of DMA transfer
0
Executes DMA transfer upon DMA start request (not held pending).
1
Holds DMA start request pending if any.
DMA transfer that has been held pending can be started by clearing the value of DWAITn to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of DWAITn is set to 1.
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
2. When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA transfer
pending for both channels (by setting the DWAIT0 and DWAIT1 bits to 1).
Remark n: DMA channel number (n = 0, 1)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011