UPD78F1502AGK-GAK-AX Datasheet, PDF (106/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 3 CPU ARCHITECTURE
Figure 3-11. Data to Be Saved to Stack Memory
PUSH rp instruction
PUSH PSW instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
Register pair lower
Register pair higher
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
CALL, CALLT instructions
(4-byte stack)
Interrupt, BRK instruction
(4-byte stack)
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
00H
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general-
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX,
BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-
register bank configuration, an efficient program can be created by switching between a register for normal processing and
a register for interrupts for each bank.
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
R01UH0004EJ0501 Rev.5.01
90
Jun 20, 2011