UPD78F1502AGK-GAK-AX Datasheet, PDF (282/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (3/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
TMRmn CKS 0
0 CCS MAST STS STS STS CIS CIS 0
0
mn
mn ERmn mn2 mn1 mn0 mn1 mn0
3
2
1
0
MD MD MD MD
mn3 mn2 mn1 mn0
MD MD MD MD
mn3 mn2 mn1 mn0
Operation mode of channel n
Count operation of TCR Independent operation
0
0
0 1/0 Interval timer mode
Counting down
Possible
0
1
0 1/0 Capture mode
Counting up
Possible
0
1
1
0 Event counter mode
Counting down
Possible
1
0
0 1/0 One-count mode
Counting down
Impossible
1
1
0
0 Capture & one-count mode
Counting up
Possible
Other than above
Setting prohibited
The operation of MDmn0 bits varies depending on each operation mode (see following table).
Cautions 1. Be sure to clear bits 14, 13, 5, and 4 to “0”.
2. Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 can
be set only to the interval mode.
3. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode and
one-count mode (when using as master).
4. Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval mode.
Remark mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
266
Jun 20, 2011