UPD78F1502AGK-GAK-AX Datasheet, PDF (291/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(e) Start timing in capture & one-count mode
<1> Writing 1 to TSpq sets TEpq = 1
<2> Enters the start trigger input wait status, and TCRpq holds the initial value.
<3> On start trigger detection, 0000H is loaded to TCRpq and count starts.
Figure 6-15. Start Timing (In Capture & One-count Mode)
fCLK
TSpq (write)
<1>
TEpq
TIN edge detection signal
Count clock ^Note
TSpq (write) hold signal
Start trigger detection signal
TCRpq
<2>
Initial value
Start trigger input wait status
<3>
0000H
Note When the capture & one-count mode is set, the operation clock (MCK) is selected as count clock (CCSpq =
0).
Caution An input signal sampling error is generated since operation starts upon start trigger detection
(The error is one count clock when TIpq is used).
(7) Timer channel stop register m (TTm)
TTm is a trigger register that is used to clear a timer counter (TCRmn) and start the counting operation of each
channel.
When a bit (TTmn) of this register is set to 1, the corresponding bit (TEmn) of timer channel enable status register
0 (TEm) is cleared to 0. TTmn is a trigger bit and cleared to 0 immediately when TEmn = 0.
TTm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TTm can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided
with timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011