UPD78F1502AGK-GAK-AX Datasheet, PDF (536/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication can be calculated by
the following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}^Note [Hz]
Note The permissible maximum frequency is the smaller of fCLK/6 and fMCK/2.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000000B to
1111111B) and therefore is 0 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
R01UH0004EJ0501 Rev.5.01
520
Jun 20, 2011