UPD78F1502AGK-GAK-AX Datasheet, PDF (685/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 16 LCD CONTROLLER/DRIVER
Caution
5. To manipulate VLCON when using the internal voltage boosting method or capacitor split
method, follow the procedure below.
A. To stop the operation of the voltage boosting/capacitor split circuit after switching display
status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting SCOC = 0.
3) Stop the operation of the voltage boosting/capacitor split circuit by setting VLCON = 0.
B. To stop the operation of the voltage boosting/capacitor split circuit during display on status:
Setting prohibited. Be sure to stop the operation of the voltage boosting/capacitor split
circuit after setting display off.
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
1) Start the operation of the voltage boosting/capacitor split circuit by setting VLCON = 1,
then wait for the voltage boosting/capacitor split wait time (see CHAPTER 31
ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status by setting
SCOC = 1.
3) Set display on by setting LCDON = 1.
(3) LCD clock control register (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
Figure 16-4. Format of LCD Clock Control Register (LCDC0)
Address: FFF42H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDC0
0
0
LCDC5
LCDC4
0
LCDC2
LCDC1
LCDC0
LCDC5
0
0
1
1
LCDC4
0
1
0
1
fSUB
fCLK/2⁶
fCLK/2⁷
fCLK/2⁸
LCD source clock (fLCD) selection
LCDC2
LCDC1
0
0
0
0
0
1
0
1
1
0
1
0
Other than above
LCDC0
0
1
0
1
0
1
fLCD/2⁴
fLCD/2⁵
fLCD/2⁶
fLCD/2⁷
fLCD/2⁸
fLCD/2⁹
Setting prohibited
LCD clock (LCDCL) selection
R01UH0004EJ0501 Rev.5.01
669
Jun 20, 2011