UPD78F1502AGK-GAK-AX Datasheet, PDF (278/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, writing to a
control register of the timer array unit is ignored, and all read values are default values.
Figure 6-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
<7>
<6>
<5>
PER0
RTCEN
DACEN
ADCEN
<4>
IICAEN^Note
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
TAU0EN
TAUmEN
0
1
Control of timer array unit m input clock
Stops supply of input clock.
• SFR used by the timer array unit m cannot be written.
• The timer array unit m is in the reset status.
Supplies input clock.
• SFR used by the timer array unit m can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
(2) Timer clock select register m (TPSm)
TPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of TPSm, and CKm0 is selected by bits 3 to 0.
Rewriting of TPSm during timer operation is possible only in the following cases.
Rewriting of PRSm00 to PRSm03 bits: Possible only when all the channels set to CKSmn = 0 are in the operation
stopped state (TEmn = 0)
Rewriting of PRSm10 to PRSm13 bits: Possible only when all the channels set to CKSmn = 1 are in the operation
stopped state (TEmn = 0)
TPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TPSm can be set with an 8-bit memory manipulation instruction with TPSmL.
Reset signal generation clears this register to 0000H.
Remark mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011