UPD78F1502AGK-GAK-AX Datasheet, PDF (292/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-16. Format of Timer Channel Stop Register m (TTm)
Address: F01B4H, F01B5H After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
TT0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0 TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
Address: F01DCH, F01DDH After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TT1
0
0
0
0
0
0
0
0
0
0
0
0 TT13 TT12 TT11 TT10
TTmn
Operation stop trigger of channel n
0 No trigger operation
1 Operation is stopped (stop trigger is generated).
Caution Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
2. mn: Unit number + Channel number
m = 0, 1, mn = 00 to 07, 10 to 13
(8) Timer input select registers 0, 1 (TIS0, TIS1)
TIS0 and TIS1 use can be set to the input signal of a timer input pin (TIpq), half the frequency of the subsystem
clock (fSUB/2), one fourth the frequency of the subsystem clock (fSUB/4), or an RTC interval interrupt (INTRTCI) as
the timer input. The timer input can be selected for each channel.
TIS0 and TIS1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
• 78K0R/LF3
Address: FFF3EH
Figure 6-17. Format of Timer Input Select Registers 0, 1 (TIS0, TIS1) (1/2)
After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
TIS0
TIS07
0
0
TIS04
TIS03
TIS02
TIS01
0
TIS00
Address: FFF4EH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
TIS1
0
0
RTCIS04 RTCIS00
0
0
0
0
R01UH0004EJ0501 Rev.5.01
276
Jun 20, 2011