UPD78F1502AGK-GAK-AX Datasheet, PDF (281/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (2/4)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
TMRmn CKS 0
0 CCS MAST STS STS STS CIS CIS 0
0
mn
mn ERmn mn2 mn1 mn0 mn1 mn0
3
2
1
0
MD MD MD MD
mn3 mn2 mn1 mn0
MAS
TER
mn
Selection of slave/master of channel n
0 Operates as slave channel with combination operation function.
1 Operates as master channel with combination operation function.
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use the odd channel as a slave channel (MASTERmn = 0).
Clear MASTERmn to 0 for a channel that is used with the independent operation function.
STS STS STS
mn2 mn1 mn0
Setting of start trigger or capture trigger of channel n
0
0
0 Only software trigger start is valid (other trigger sources are unselected).
0
0
1 Valid edge of TIpq pin input signal, fSUB/2, fSUB/4, or INTRTC1 is used as both the start trigger
and capture trigger.
0
1
0 Both the edges of TIpq pin input signal, fSUB/2, fSUB/4, or INTRTC1 are used as a start trigger
and a capture trigger.
1
0
0 Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the combination operation function).
Other than above Setting prohibited
CIS CIS
mn1 mn0
Selection of valid edge of TIpq pin input signal , fSUB/2, fSUB/4, or INTRTC1
(the timer input used with channel x is selected by using TISm register).
0
0 Falling edge
0
1 Rising edge
1
0 Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
1
1 Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
265
Jun 20, 2011