UPD78F1502AGK-GAK-AX Datasheet, PDF (835/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
(b) When LVI default start function enabled is set (LVIOFF = 0)
• When starting operation
<1> Start in the following initial setting state.
• Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
• Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD))
• Set the low-voltage detection level selection register (LVIS) to 0EH (default value: VLVI = 2.07 V ±0.1
V ).
• Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
• Set bit 0 (LVIF) of LVIM to 0 (Detects falling edge “Supply voltage (VDD) ≥ detection voltage (VLVI)”)
<2> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default
value).
<3> Release the interrupt mask flag of LVI (LVIMK).
<4> Execute the EI instruction (when vector interrupts are used).
Figure 24-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <3> above.
• When stopping operation
Be sure to clear (0) LVION by using a 1-bit memory manipulation instruction.
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may
become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011