UPD78F1502AGK-GAK-AX Datasheet, PDF (262/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (6/6)
(13) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• HALT mode (K) set while CPU is operating with 20 MHz internal high-speed oscillation clock (J)
(B) → (E)
(C) → (F)
(D) → (G)
(J) → (K)
Status Transition
Executing HALT instruction
Setting
(14) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(B) → (H)
(C) → (I)
(Setting sequence)
Status Transition
In X1 oscillation
External main
system clock
Stopping peripheral
functions that cannot
operate in STOP
mode
Setting
−
Sets the OSTS
register
−
Executing STOP
instruction
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Jun 20, 2011