UPD78F1502AGK-GAK-AX Datasheet, PDF (309/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at master channel timer interrupt
(INTTMpq) generation is delayed by 1 count clock by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave channels are set as follows.
• Master channel: TOEpq = 1, TOMpq = 0, TOLpq = 0
• Slave channel: TOEpr = 1, TOMpr = 1, TOLpr = 0
Figure 6-31. Set/Reset Timing Operating Statuses
fCLK
Count clock
Master channel
INTTMpq
to_reset
(Internal signal)
TOpq pin/
TOpq
to_set
(Internal signal)
Toggle
Slave channel
INTTMpr
Delays to_reset by 1 count
clock with slave channel
to_reset
(Internal signal)
TOpr pin/
TOpr
Set
Reset
Remarks 1. to_reset: TOpq pin reset/toggle signal
to_set: TOpq pin set signal
2. pq: Unit number + Channel number (only for channels provided with timer I/O pins)
<1> 78K0R/LF3:
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
<2> 78K0R/LG3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
<3> 78K0R/LH3:
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
q < r ≤ 7 (where r is a consecutive integer greater than q)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
q < r ≤ 3 (where r is a consecutive integer greater than q)
R01UH0004EJ0501 Rev.5.01
293
Jun 20, 2011