UPD78F1502AGK-GAK-AX Datasheet, PDF (925/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (8/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2)
Parameter Symbol
Conditions
MIN.
Transfer
rate
transmission
4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fCLK = 16.8 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 1.4 kΩ, Vb =
2.7 V
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V
fCLK = 19.2 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 2.7 kΩ, Vb =
2.3 V
TYP. MAX.
Note 1
2.8 ^{Note 2}
Note 3
1.2 ^{Note 4}
Unit
bps
Mbps
bps
Mbps
Notes 1.
The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD = EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate =
1
{−Cb × Rb × ln (1−
2.2
Vb
)} × 3
[bps]
Baud rate error (theoretical value) =
1
2.2
−{ −Cb × Rb × ln (1 −
)}
Transfer rate × 2
Vb
(
1
Transfer rate
) ×Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum
transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD = EVDD < 4.0 V and 2.3 V ≤ Vb < 2.7 V
Maximum transfer rate =
1
{−Cb × Rb × ln (1−
2.0
Vb
)} × 3
[bps]
Baud rate error (theoretical value) =
1
2.0
−{ −Cb × Rb × ln (1 −
)}
Transfer rate × 2
Vb
(
1
Transfer rate
) ×Number of transferred bits
× 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) mode for TxDq by
using the PIMg and POMx registers.
(Remarks are given on the next page.)
R01UH0004EJ0501 Rev.5.01
909
Jun 20, 2011