UPD78F1502AGK-GAK-AX Datasheet, PDF (328/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-47. Example of Set Contents of Registers When Frequency Divider Is Used
(a) Timer mode register pq (TMRpq)
15 14 13 12 11 10 9
8
7
6
5
TMRpq CKSpq
1/0 0
MAS
CCSpq
STSpq2 STSpq1 STSpq0 CISpq1 CISpq0
TERpq
0
1
0
0
0
0 1/0 1/0 0
4
3
2
1
0
MDpq3 MDpq2 MDpq1 MDpq0
0
0
0
0 1/0
Operation mode of channel q
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMpq nor inverts
timer output when counting is started.
1: Generates INTTMpq and inverts timer
output when counting is started.
Selection of TIpq pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when independent function is selected.
Count clock selection
1: Selects the TIpq pin input valid edge.
Operation clock selection
0: Selects CKp0 as operation clock of channel q.
1: Selects CKp1 as operation clock of channel q.
(b) Timer output register p (TOp)
Bit q
TOp
TOpq
1/0
0: Outputs 0 from TOpq.
1: Outputs 1 from TOpq.
(c) Timer output enable register p (TOEp)
Bit q
TOEp
TOEpq
1/0
0: Stops the TOpq output operation by counting operation.
1: Enables the TOpq output operation by counting operation.
(d) Timer output level register p (TOLp)
Bit q
TOLp
TOLpq
0
0: Cleared to 0 when TOMpq = 0 (toggle mode)
(e) Timer output mode register p (TOMp)
Bit q
TOMp
TOMpq
0
0: Sets toggle mode.
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011