UPD78F1502AGK-GAK-AX Datasheet, PDF (601/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (1/4)
Address: F0230H After reset: 00H R/W
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
IICCTL0 IICE
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
IICE
I²C operation enable
0
Stop operation. Reset the IICA status register (IICS)^{Note 1}. Stop internal operation.
1
Enable operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE = 0)
Condition for setting (IICE = 1)
• Cleared by instruction
• Reset
• Set by instruction
LREL^{Notes 2,3}
Exit from communications
0
Normal operation
1
This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICCTL0) and IICA status register (IICS) are cleared to 0.
• STT • SPT • MSTS • EXC • COI • TRC • ACKD • STD
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL = 0)
Condition for setting (LREL = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
WREL^{Notes 2,3}
Wait cancellation
0
Do not cancel wait
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC =
1), the SDA0 line goes into the high impedance state (TRC = 0).
Condition for clearing (WREL = 0)
Condition for setting (WREL = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
Notes 1. The IICS register, the STCF and IICBSY bits of the IICF register, and the CLD and DAD
bits of the IICCTL1 register are reset.
2. The signal of this bit is invalid while IICE is 0.
3. When the LREL and WREL bits are read, 0 is always read.
Caution
If the operation of I²C is enabled (IICE = 1) when the SCL0 line is at high level, the SDA0 line
is at low level, and DFC of the IICCTL1 register is 1, a start condition will be inadvertently
detected immediately. Immediately after enabling I²C to operate (IICE = 1), set LREL (1) by
using a 1-bit memory manipulation instruction.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011