UPD78F1502AGK-GAK-AX Datasheet, PDF (521/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.5.5 Slave reception
Slave reception is that the 78K0R/Lx3 microcontrollers receive data from another device in the state of a transfer clock
being input from another device.
3-Wire Serial I/O
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
CSI00
CSI01
CSI10
CSI20
Channel 0 of SAU0
Channel 1 of SAU0
Channel 2 of SAU0
Channel 0 of SAU1
SCK00, SI00
SCK01, SI01
SCK10, SI10
SCK20, SI20
INTCSI00
INTCSI01
INTCSI10
INTCSI20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. fMCK/6 [MHz]^{Notes 1, 2}
Selectable by DAPmn bit
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally and
used, the fastest transfer rate is fMCK/6 [MHz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. For 78K0R/LF3, CSI00 and CSI01 are not mounted.
3. For 78K0R/LG3, CSI01 is not mounted.
R01UH0004EJ0501 Rev.5.01
505
Jun 20, 2011