UPD78F1502AGK-GAK-AX Datasheet, PDF (607/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-7. Format of IICA Status Register (IICS) (3/3)
ACKD
Detection of acknowledge (ACK)
0
Acknowledge was not detected.
1
Acknowledge was detected.
Condition for clearing (ACKD = 0)
Condition for setting (ACKD = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• After the SDA0 line is set to low level at the rising
edge of SCL0’s ninth clock
STD
Detection of start condition
0
Start condition was not detected.
1
Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD = 0)
Condition for setting (STD = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
following address transfer
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When a start condition is detected
SPD
Detection of stop condition
0
Stop condition was not detected.
1
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Condition for clearing (SPD = 0)
Condition for setting (SPD = 1)
• At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a
start condition
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When a stop condition is detected
Remark LREL: Bit 6 of IICA control register 0 (IICCTL0)
IICE: Bit 7 of IICA control register 0 (IICCTL0)
(4) IICA flag register (IICF)
This register sets the operation mode of I²C and indicates the status of the I²C bus.
IICF can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are read-
only.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I²C is disabled (bit 7 (IICE) of IICA control register 0
(IICCTL0) = 0). When operation is enabled, the IICF register can be read.
Reset signal generation clears this register to 00H.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011