UPD78F1502AGK-GAK-AX Datasheet, PDF (465/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(3) Serial mode register mn (SMRmn)
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock (MCK),
specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or
I²C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART
mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can
be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Figure 14-6. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
SMRmn CKS CCS 0
0
0
0
0 STS 0 SIS 1
0
mn mn
mn
mn0
3
2
1
0
0 MD MD MD
mn2 mn1 mn0
CKS
mn
Selection of operation clock (MCK) of channel n
0 Prescaler output clock CKm0 set by SPSm register
1 Prescaler output clock CKm1 set by SPSm register
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
CCS
mn
Selection of transfer clock (TCLK) of channel n
0 Divided operation clock MCK specified by CKSmn bit
1 Clock input from SCK pin (slave transfer in CSI mode)
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
STS
Selection of start trigger source
mn
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I²C).
1 Valid edge of RXD pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
449
Jun 20, 2011