UPD78F1502AGK-GAK-AX Datasheet, PDF (881/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (6/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
16-bit
MOVW AX, ES:[HL + byte]
3
data
transfer
ES:[HL + byte], AX
3
AX, ES:word[B]
4
2
5 AX ← ((ES, HL) + byte)
2
− ((ES, HL) + byte) ← AX
2
5 AX ← ((ES, B) + word)
ES:word[B], AX
4
2
− ((ES, B) + word) ← AX
AX, ES:word[C]
4
2
5 AX ← ((ES, C) + word)
ES:word[C], AX
4
2
− ((ES, C) + word) ← AX
AX, ES:word[BC]
4
2
5 AX ← ((ES, BC) + word)
ES:word[BC], AX
4
2
− ((ES, BC) + word) ← AX
BC, ES:!addr16
4
2
5 BC ← (ES, addr16)
DE, ES:!addr16
4
2
5 DE ← (ES, addr16)
HL, ES:!addr16
4
2
5 HL ← (ES, addr16)
XCHW AX, rp
Note 3
1
1
− AX ←→ rp
ONEW AX
1
1
− AX ← 0001H
BC
1
1
− BC ← 0001H
CLRW AX
1
1
− AX ← 0000H
BC
1
1
− BC ← 0000H
8-bit
ADD
operation
A, #byte
saddr, #byte
2
1
− A, CY ← A + byte
3
2
− (saddr), CY ← (saddr) + byte
×××
×××
A, r
Note 4
2
1
− A, CY ← A + r
×××
r, A
2
1
− r, CY ← r + A
×××
A, saddr
2
1
− A, CY ← A + (saddr)
×××
A, !addr16
3
1
4 A, CY ← A + (addr16)
×××
A, [HL]
1
1
4 A, CY ← A + (HL)
×××
A, [HL + byte]
2
1
4 A, CY ← A + (HL + byte)
×××
A, [HL + B]
2
1
4 A, CY ← A + (HL + B)
×××
A, [HL + C]
2
1
4 A, CY ← A + (HL + C)
×××
A, ES:!addr16
4
2
5 A, CY ← A + (ES, addr16)
×××
A, ES:[HL]
2
2
5 A,CY ← A + (ES, HL)
×××
A, ES:[HL + byte]
3
2
5 A,CY ← A + ((ES, HL) + byte)
×××
A, ES:[HL + B]
3
2
5 A,CY ← A + ((ES, HL) + B)
×××
A, ES:[HL + C]
3
2
5 A,CY ← A + ((ES, HL) + C)
×××
Notes 1.
2.
3.
4.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Except rp = AX
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
865
Jun 20, 2011