UPD78F1502AGK-GAK-AX Datasheet, PDF (982/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(10/39)
Page
Subsystem XT1/P123,
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release. p.237 _†
clock
XT2/P124
control
Subsystem clock When the subsystem clock is used as the CPU clock, the subsystem clock is also pp.237, _†
supplied to the peripheral hardware (except the real-time counter, timer array unit 238
(when fSUB/2, fSUB/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is
selected as the count clock), clock output/buzzer output, and watchdog timer). At
this time, the operations of the A/D converter and IICA are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing
the various peripheral hardware as well as CHAPTER 31 ELECTRICAL
SPECIFICATIONS.
The CMC register can be written only once after reset release, by an 8-bit memory p.238 _†
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time. For EXCLK and OSCSEL bits, see 5.6.1 (1) Example of setting
procedure when oscillating the X1 clock or 5.6.1 (2) Example of setting procedure
when using the external main system clock.
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the p.238 _†
peripheral hardware if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
p.238 _†
CPU clock
−
Set the clock after the supply voltage has reached the operable voltage of the clock pp.241 _†
status
to be set (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
242, 245
transition
Timer
−
Channel 5 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval p.251 _†
array unit
timer.
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be used only as an interval p.251 _†
timer, for PWM output (master channel), and for one-shot pulse output (master
channel when software trigger start is selected).
Channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 and 78K0R/LG3 can be used p.251 _†
only as interval timers.
Channels 1, 5 to 7 of timer array unit 0 and channels 0 to 3 of timer array unit 1 p.251 _†
cannot be used as frequency dividers.
TCRmn:
The count value is not captured to TDRmn even when TCRmn is read.
p.255 _†
Timer/counter
register mn
TDRmn: Timer TDRmn does not perform a capture operation even if a capture trigger is input, when p.260 _†
data register mn it is set to the compare function.
PER0:
When setting the timer array unit, be sure to set TAUmEN to 1 first. If TAUmEN = 0, p.262 _†
Peripheral
writing to a control register of the timer array unit is ignored, and all read values are
enable register 0 default values.
TPSm: Timer Be sure to clear bits 15 to 8 to “0”.
p.268 _†
clock select
register m
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011