UPD78F1502AGK-GAK-AX Datasheet, PDF (406/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
10.3 Registers Used in A/D Converter
The A/D converter uses the following ten registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D converter mode register 1 (ADM1)
• Analog reference voltage control register (ADVRC)
• 12-bit A/D conversion result register (ADCR) (μ PD78F150xA only)
<R>
• 10-bit A/D conversion result register (ADCR) (μ PD78F151xA only)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• A/D port configuration register (ADPC)
• Port mode registers 2, 15 (PM2, PM15)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
<7>
<6>
<5>
PER0
RTCEN
DACEN
ADCEN
<4>
IICAEN ^Note
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
TAU0EN
ADCEN
0
1
Control of A/D converter, operational amplifier, and voltage reference input clock
Stops supply of input clock.
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
• SFR used by the A/D converter can, operational amplifier, and voltage reference can be
read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Caution When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
control register of the A/D converter is ignored, and, even if the register is read, only the default
value is read.
R01UH0004EJ0501 Rev.5.01
390
Jun 20, 2011