UPD78F1502AGK-GAK-AX Datasheet, PDF (669/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control) ^H
MSTS
(communication status) ^H
STT
(ST trigger)
SPT
(SP trigger)
L
WREL
(wait cancellation) ^L
INTIICA
(interrupt)
TRC
(transmit/receive) ^H
Bus line
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
Slave side
<8>
D13 D12 D11 D10 ^ACK
<7>
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection) ^L
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control) ^H
MSTS
(communication status) ^L
WREL
(wait cancellation)
<i>
INTIICA
(interrupt)
TRC
(transmit/receive) ^L
<iii>
<ii>
Note 1
Restart condition
AD6 AD5 AD4 AD3 AD2 AD1
Slave address
Note 2
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Make sure that the time between the rise of the SCL0 pin signal and the generation of the start
condition after a restart condition has been issued is at least 4.7 μs when specifying standard mode and
at least 0.6 μs when specifying fast mode.
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
R01UH0004EJ0501 Rev.5.01
653
Jun 20, 2011