UPD78F1502AGK-GAK-AX Datasheet, PDF (675/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-33. Example of Slave to Master Communication
(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Data ~ data ~ stop condition
Master side
IICA
ACKD
(ACK detection)
WTIM
(8 or 9 clock wait)
ACKE
(ACK control)
MSTS
(communication status)
STT
(ST trigger)
L
SPT
(SP trigger)
WREL
(wait cancellation)
INTIICA
(interrupt)
TRC
(transmit/receive) ^L
Note 1
<9>
<14>
Note 1 ^<17>
<15>
Bus line
Stop conditon
SCL0 (bus)
(clock line)
SDA0 (bus)
(data line)
Slave side
<8>
<11>
D150 ^ACK
<10>
<13>
D167 D166 D165 D164 D163 D162 D161 D160
IICA
ACKD
(ACK detection)
STD
(ST detection)
L
SPD
(SP detection)
WTIM
(8 or 9 clock wait)
H
ACKE
(ACK control)
H
MSTS
(communication ^L
status)
WREL
(wait cancellation)
INTIICA
(interrupt)
<12> Note 3
TRC
(transmit/receive)
<16>
Note 2
NACK
<19>
<18>
Notes 1, 4
Note 4
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel a wait state, write “FFH” to IICA or set the WREL bit.
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
after a stop condition has been issued is at least 4.0 μs when specifying standard mode and at least 0.6
μs when specifying fast mode.
3. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
4. If a wait state during slave transmission is canceled by setting the WREL bit, the TRC bit will be cleared.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011