UPD78F1502AGK-GAK-AX Datasheet, PDF (834/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-8. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Supply voltage (VDD)
VLVI
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Note 3
Note 3
LVIMK flag
(set by software)
LVISEL flag
(set by software) L
<1>
Note 1
<8> Cleared by software
<3>
LVION flag
(set by software)
<2>
<4>
<5> Wait time
LVIF flag
INTLVI
Note 2
<6>
LVIIF flag
LVIMD flag
(set by software) ^L
Note 2
<7>
Note 2 Cleared by software
Time
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
Remarks 1. <1> to <8> in Figure 24-8 above correspond to <1> to <8> in the description of “When starting
operation” in 24.4.2 (1) (a) When LVI default start function stopped is set (LVIOFF = 1).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
818
Jun 20, 2011