UPD78F1502AGK-GAK-AX Datasheet, PDF (154/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
<R>
P20/ANI0/AMP0-
P21/ANI1/AMP0O
P22/ANI2/AMP0+
P23/ANI3/AMP1-
P24/ANI4/AMP1O
P25/ANI5/AMP1+
P26/ANI6/AMP2-
P27/ANI7/AMP2O
78K0R/LF3
(80 pins)
P26/ANI6
−
μ PD78F150xA
78K0R/LG3
78K0R/LH3
(100 pins)
(128 pins)
√
√
√
√
√
√
√
√
μ PD78F151xA
78K0R/LF3
(80 pins)
78K0R/LG3
(100 pins)
78K0R/LH3
(128 pins)
P20/ANI0
P20/ANI1
P20/ANI2
P20/ANI3
P20/ANI4
P20/ANI5
P26/ANI6
−
P27/ANI7
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input, and operational amplifier I/O.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as digital input pins, set them in the digital I/O mode by using the A/D
port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as digital output pins, set them in the digital I/O mode by using ADPC
and in the output mode by using PM2.
To use P20/ANI0/AMP0- to P27/ANI7/AMP2O as analog input pins, set them in the analog input mode by using the A/D
port configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the upper bit.
All P20/ANI0/AMP0- to P27/ANI7/AMP2O are set in the digital input mode when the reset signal is generated.
Figures 4-7 to 4-9 show block diagrams of port 2.
Caution Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 2 is used as a digital port.
R01UH0004EJ0501 Rev.5.01
138
Jun 20, 2011