UPD78F1502AGK-GAK-AX Datasheet, PDF (458/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-1 shows the block diagram of serial array unit 0.
Figure 14-1. Block Diagram of Serial Array Unit 0
Serial output register 0 (SO0)
0
0
0
0
1 CKO02 CKO01 CKO00 0
0
0
Peripheral enable
register 0 (PER0)
SAU0EN
PRS
013
Serial clock select register 0 (SPS0)
PRS PRS PRS PRS PRS PRS
012 011 010 003 002 001
PRS
000
4
4
fCLK
INTTM02
Prescaler
fCLK/2⁰ to fCLK/2¹¹
fCLK/2⁰ to
fCLK/2¹¹
0
1 SO02 SO01 SO00
Noise filter enable
register 0 (NFEN0)
SNFEN SNFEN
10
00
SE03 SE02 SE01 SE00 ^{Serial channel enable}
status register 0 (SE0)
SS03 SS02 SS01
SS00
Serial channel start
register 0 (SS0)
ST03 ST02 ST01
ST00
Serial channel stop
register 0 (ST0)
0
SOE02 SOE01 SOE00
Serial output enable
register 0 (SOE0)
Serial output level
0 SOL02 0 SOL00 _{register 0 (SOL0)}
Selector
Selector
Serial clock I/O pin
(when CSI00: SCK00)
Serial data input pin
(when CSI00: SI00)
(when UART0: RxD0)
When UART0
Channel 0
CK01
CK00
Serial data register 00 (SDR00)
(Clock division setting block) (Buffer register block)
Edge
SCK
detection
MCK
TCLK
Shift register
Output latch
(P82)
PM82
Output
controller
PM80
Output latch
(P80)
Noise
elimination
enabled/
disabled
Edge/level
detection
Communication controller
Mode selection
CSI00 or UART0
(for transmission)
Interrupt
controller
Serial flag clear trigger
register 00 (SIR00)
FECT PECT OVCT
00 00 00
Clear
Serial data output pin
(when CSI00: SO00)
(when UART0: TXD0)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
SNFEN00
CKS00 CCS00 STS00 MD002 MD001
Serial mode register 00 (SMR00)
TXE RXE DAP CKP EOC PTC PTC DIR SLC SLC DLS DLS DLS
00 00 00 00 00 001 000 00 001 000 002 001 000
Serial communication operation setting register 00 (SCR00)
Error controller
Error
information
TSF BFF FEF PEF OVF
00
00 00
00
00
Serial status register 00 (SSR00)
Serial clock I/O pin
(when CSI01: SCK01)
Serial data input pin
(when CSI01: SI01)
CK01
Channel 1
CK00
Selector
Edge/level
detection
Communication controller
Mode selection
CSI01 or UART0
(for reception)
Error controller
Serial data output pin
(when CSI01: SO01)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Serial transfer error interrupt
(INTSRE0)
Serial clock I/O pin
(when CSI10: SCK10)
(when IIC10: SCL10)
Serial data input pin
(when CSI10: SI10)
(when IIC10: SDA10)
(when UART1: RXD1)
Channel 2
CK01
CK00
Noise
elimination
enabled/
disabled
SNFEN10
Edge/level
detection
Communication controller
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
Serial data output pin
(when CSI10: SO10)
(when IIC10: SDA10)
(when UART1: TXD1)
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
When UART1
Channel 3
CK01
CK00
Edge/level
detection
Communication controller
Mode selection
UART1
(for reception)
Remarks 1. For 78K0R/LF3, the channels 0 and 1 are not mounted.
2. For 78K0R/LG3, CSI01 is not mounted.
Error controller
Serial transfer end interrupt
(when UART1: INTSR1)
Serial transfer error interrupt
(INTSRE1)
R01UH0004EJ0501 Rev.5.01
442
Jun 20, 2011