UPD78F1502AGK-GAK-AX Datasheet, PDF (686/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 16 LCD CONTROLLER/DRIVER
Cautions 1. Bits 3, 6, and 7 must be set to 0.
2. Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost method has
been set.
Remark fCLK: CPU/Peripheral hardware clock frequency
fSUB: Subsystem clock frequency
(4) LCD boost level control register (VLCD)
This register is used to select the reference voltage that is to be generated when operating the voltage boost
circuit (contrast adjustment). The reference voltage can be selected from 20 stages.
VLCD is set using an 8-bit memory manipulation instruction.
Reset signal generation sets VLCD to 0FH.
Figure 16-5. Format of LCD Boost Level Control Register (VLCD)
Address: FFF43H After reset: 0FH R/W
Symbol
7
6
5
VLCD
0
0
0
4
VLCD4
3
VLCD3
2
VLCD2
1
VLCD1
0
VLCD0
VLCD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
VLCD3
VLCD2
VLCD1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
Other than above
VLCD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference voltage
VLC0 voltage
selection
1/3 bias
(contrast adjustment)
1/4 bias
1.75 V
1.70 V
5.25 V
5.10 V
Setting
prohibited ^Note
1.65 V
4.95 V
1.60 V
4.80 V
1.55 V
4.65 V
1.50 V
4.50 V
1.45 V
4.35 V
1.40 V
4.20 V
1.35 V
4.05 V
1.30 V
3.90 V 5.20 V
1.25 V
3.75 V 5.00 V
1.20 V
3.60 V 4.80 V
1.15 V
3.45 V 4.60 V
1.10 V
3.30 V 4.40 V
1.05 V
3.15 V 4.20 V
1.00 V
3.00 V 4.00 V
(default)
0.95 V
2.85 V 3.80 V
0.90 V
2.70 V 3.60 V
0.85 V
2.55 V 3.40 V
0.80 V
2.40 V 3.20 V
Setting prohibited
Note These settings are prohibited because VLC0 > 5.5 V.
R01UH0004EJ0501 Rev.5.01
670
Jun 20, 2011