UPD78F1502AGK-GAK-AX Datasheet, PDF (793/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
Table 21-1. Operating Statuses in HALT Mode (1/3)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fIH) or 20
MHz Internal High-Speed
Oscillation Clock (fIH20)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEX)
System clock
Clock supply to the CPU is stopped
Main system clock fIH
Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX
Status before HALT mode
Operation continues (cannot Cannot operate
was set is retained
be stopped)
fEX
Cannot operate
Operation continues (cannot
be stopped)
Subsystem clock fXT
Status before HALT mode was set is retained
fIL
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
CPU
Operation stopped
Flash memory
Operation stopped
RAM
Status before HALT mode was set is retained at voltage higher than POC detection voltage.
Port (latch)
Status before HALT mode was set is retained
Timer array unit (TAU)
Operable
Real-time counter (RTC)
Watchdog timer
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
Operable
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
Remarks 1.
2.
fIH: Internal high-speed oscillation clock, fIH20:
fX: X1 oscillation clock,
fEX:
fXT: XT1 oscillation clock,
fIL:
The functions mounted depend on the product.
Functions.
20 MHz internal high-speed oscillation clock
External main system clock
Internal low-speed oscillation clock
Refer to 1.4 Block Diagram and 1.5 Outline of
R01UH0004EJ0501 Rev.5.01
777
Jun 20, 2011