UPD78F1502AGK-GAK-AX Datasheet, PDF (1011/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(39/39)
Page
Electrical During
specifications communication
at different
potential (2.5 V,
3 V) (CSI mode)
(master mode,
SCKp... internal
clock output)
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(slave mode,
SCKp... external
clock input)
During
communication
at different
potential (2.5 V,
3 V) (simplified
I²C mode)
VR circuit
Recommended
−
soldering
condition
Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) pp.912 _†
mode for SOp and SCKp by using the PIMg and POMx registers.
to 914
Select the TTL input buffer for SIp and SCKp and the N-ch open drain output (VDD pp.916, _†
tolerance) mode for SOp by using the PIMg and POMx registers.
917
Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for pp.918, _†
SDAr and the N-ch open drain output (VDD tolerance) mode for SCLr by using the 919
PIMg and POMx registers.
Connect the VREFOUT pin to GND via a tantalum capacitor (capacitance: 10 p.923 _†
μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)) and a ceramic capacitor
(capacitance: 0.1 μF±30 %, ESR: 2 Ω (max.), ESL: 10 nH (max.)).
The μPD78F1500A to 78F1508A have an on-chip debug function, which is provided pp.938, _†
for development and evaluation. Do not use the on-chip debug function in products 939
designated for mass production, because the guaranteed number of rewritable times
of the flash memory may be exceeded when this function is used, and product
reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
R01UH0004EJ0501 Rev.5.01
995
Jun 20, 2011