UPD78F1502AGK-GAK-AX Datasheet, PDF (409/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
Table 10-2. A/D Conversion Time Selection
A/D Converter Mode Register (ADM)
FR2 FR1 FR0 LV1 LV0
Mode
Conversion Time Selection
fCLK =
fCLK =
fCLK =
fCLK =
Conversion
Clock (fAD)
1 MHz
8 MHz
10 MHz
20 MHz
0
0
0
0
0
Normal 240/fCLK Setting
30 μs
24 μs
12 μs
fCLK/12
0
0
1
0
1
0
mode 1
Note 1
160/fCLK prohibited
120/fCLK
20 μs
15 μs
16 μs
12 μs
8 μs
6 μs
fCLK/8
fCLK/6
0
1
1
100/fCLK
12.5 μs
10 μs
5 μs
fCLK/5
1
0
0
80/fCLK
10 μs
8 μs
Setting
fCLK/4
1
0
1
60/fCLK
7.5 μs
6 μs
prohibited fCLK/3
1
1
0
40/fCLK 40 μs
5 μs
Setting
fCLK/2
1
1
1
20/fCLK 20 μs
Setting
prohibited
fCLK
prohibited
0
0
0
0
1
Normal 240/fCLK Setting
30 μs
24 μs
12 μs
fCLK/12
0
0
1
0
1
0
mode 2
Note 2
160/fCLK prohibited
120/fCLK
20 μs
15 μs
16 μs
12 μs
8 μs
6 μs
fCLK/8
fCLK/6
0
1
1
100/fCLK
12.5 μs
10 μs
5 μs
fCLK/5
1
0
0
80/fCLK
10 μs
8 μs
Setting
fCLK/4
1
0
1
60/fCLK
7.5 μs
6 μs
prohibited fCLK/3
1
1
0
40/fCLK 40 μs
5 μs
Setting
fCLK/2
1
1
1
20/fCLK 20 μs
Setting
prohibited
fCLK
prohibited
0
0
0
1
0
Low
300/fCLK Setting
37.5 μs
30 μs
15 μs ^{Note 4} fCLK/12
0
0
1
voltage 200/fCLK prohibited 25 μs
20 μs ^{Note 4} 10 μs ^{Note 4} fCLK/8
0
1
0
mode 150/fCLK
18.8 μs ^{Note 4} 15 μs ^{Note 4} 7.5 μs ^{Note 4} fCLK/6
0
1
1
Note 3
125/fCLK
15.6 μs ^{Note 4} 12.5 μs ^{Note 4} 6.25 μs ^{Note 4} fCLK/5
1
0
0
100/fCLK
12.5 μs ^{Note 4} 10 μs ^{Note 4} Setting
fCLK/4
1
0
1
75/fCLK
9.38 μs ^{Note 4} 7.5 μs ^{Note 4} prohibited fCLK/3
1
1
0
50/fCLK 50 μs
6.25 μs ^{Note 4} Setting
fCLK/2
1
1
1
25/fCLK 25 μs
Setting
prohibited
fCLK
prohibited
Other than above
Setting prohibited
Notes 1. Normal mode 1: 2.7 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is stopped.
2. Normal mode 2: 2.3 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is operating.
3. Low voltage mode: 1.8 V ≤ AVDD0 ≤ 5.5 V, when operation of the input gate voltage boost circuit for the A/D
converter is operating.
4. When TA = 0 to 50°C and 2.3 V ≤ AVDD0 ≤ 3.6 V.
Caution When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage mode (LV1 = 1, LV0
= 0), enable the input gate voltage boost circuit for the A/D converter by using the analog reference
voltage control register (ADVRC), and then set ADCE and ADCS to 1. After the voltage boost circuit
stabilization time (10 μs) passes after the input gate voltage boost circuit for the A/D converter has
been enabled, set ADCS to 1.
Remark fCLK: CPU/peripheral hardware clock frequency
R01UH0004EJ0501 Rev.5.01
393
Jun 20, 2011