UPD78F1502AGK-GAK-AX Datasheet, PDF (978/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(6/39)
Page
Clock
generator
CMC: Clock
The XT1 oscillator is designed as a low-gain circuit for achieving low-power pp.210, _†
operation mode consumption. Note the following points when designing the XT1 oscillator.
211
control register • The pins and circuit board include parasitic capacitance. Therefore, confirm that
there are no problems by performing oscillation evaluation on the circuit board to
be actually used.
• When low-consumption oscillation or super-low-consumption oscillation is
selected, lower power consumption than when selecting normal oscillation can be
achieved. However, in this case, the XT1 oscillation margin is reduced, so
perform sufficient oscillation evaluation of the resonator to be used for XT1
oscillation before using the resonator.
• Keep the wiring length between the XT1 and XT2 pins and resonator as short as
possible and parasitic capacitance and wire resistance as small as possible. This
is particularly important when super-low-consumption oscillation (AMPHS1 = 1) is
selected.
• Configure the circuit board by using material with little parasitic capacitance and
wire resistance.
• Place a ground pattern that has the same potential as VSS (if possible) around the
XT1 oscillator.
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator
with other signal lines. Do not route the signal lines near a signal line through
which a high fluctuating current flows.
• Moisture absorption by the circuit board and condensation on the board in a
highly humid environment may cause the impedance between the XT1 and XT2
pins to drop and disable oscillation. When using the circuit board in such an
environment, prevent the circuit board from absorbing moisture by taking
measures such as coating the circuit board.
• Coat the surface of the circuit board by using material that does not generate
capacitance or leakage between the XT1 and XT2 pins.
CSC: Clock
After reset release, set the clock operation mode control register (CMC) before p.211 _†
operation status starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
control register To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the p.212 _†
X1 clock by using the oscillation stabilization time counter status register (OSTC).
Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the p.212 _†
CSC register.
The setting of the flags of the register to stop clock oscillation (invalidate the external p.212 _†
clock input) and the condition before clock oscillation is to be stopped are as follows.
OSTC:
After the above time has elapsed, the bits are set to 1 in order from MOST8 and p.213 _†
Oscillation
remain 1.
stabilization time The oscillation stabilization time counter counts up to the oscillation stabilization time p.213 _†
counter status set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
register
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
R01UH0004EJ0501 Rev.5.01
962
Jun 20, 2011