UPD78F1502AGK-GAK-AX Datasheet, PDF (466/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
Figure 14-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol
15 14 13 12 11 10 9
8
7
6
5
4
SMRmn CKS CCS 0
0
0
0
0 STS 0 SIS 1
0
mn mn
mn
mn0
3
2
1
0
0 MD MD MD
mn2 mn1 mn0
SIS
Controls inversion of level of receive data of channel n in UART mode
mn0
0 Falling edge is detected as the start bit.
The input communication data is captured as is.
1 Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD MD
mn2 mn1
0
0 CSI mode
0
1 UART mode
1
0 Simplified I²C mode
1
1 Setting prohibited
Setting of operation mode of channel n
MD
Selection of interrupt source of channel n
mn0
0 Transfer end interrupt
1 Buffer empty interrupt
For successive transmission, the next transmit data is written by setting MDmn0 to 1 when SDRmn data has run
out.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
450
Jun 20, 2011