UPD78F1502AGK-GAK-AX Datasheet, PDF (623/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.12 Arbitration
When several master devices simultaneously generate a start condition (when STT is set to 1 before STD is set to 1),
communication among the master devices is performed as the number of clocks are adjusted until the data differs. This
kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD) in the IICA status register (IICS) is
set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance,
which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
condition is detected, etc.) and the ALD = 1 setting that has been made by software.
For details of interrupt request timing, see 15.5.8 Interrupt request (INTIICA) generation timing and wait control.
Remark STD: Bit 1 of IICA status register (IICS)
STT: Bit 1 of IICA control register 0 (IICCTL0)
Figure 15-21. Arbitration Timing Example
Master 1
SCL0
SDA0
Master 2
SCL0
Hi-Z
Hi-Z
Master 1 loses arbitration
SDA0
Transfer lines
SCL0
SDA0
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Jun 20, 2011