UPD78F1502AGK-GAK-AX Datasheet, PDF (985/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(13/39)
Page
Operation of Input pulse
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit p.315 _†
timer array interval
of the TMRpq register, so an error equal to the number of operating clocks occurs.
unit as
measurement
independent Input signal
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit p.319 _†
channel
high-/low-level of the TMRpq register, so an error equal to the number of operating clocks occurs.
width
measurement
Operation PWM function To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a p.323 _†
of plural
write access is necessary two times. The timing at which the values of TDRmn and
channels of
TDRmp are loaded to TCRmn and TCRmp is upon occurrence of INTTMmn of the
timer array
master channel. Thus, when rewriting is performed split before and after occurrence
unit
of INTTMmn of the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, therefore,
be sure to rewrite both the registers immediately after INTTMmn is generated from
the master channel.
One-shot pulse The timing of loading of TDRmn of the master channel is different from that of
p.330 _†
output function TDRmp of the slave channel. If TDRmn and TDRmp are rewritten during operation,
therefore, an illegal waveform is output. Be sure to rewrite TDRmn and TDRmp after
INTTMmn of the channel to be rewritten is generated.
Multiple PWM To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1, p.337 _†
output function write access is necessary at least twice. Since the values of TDRmn and TDRmp
are loaded to TCRmn and TCRmp after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn
from the master channel, the TOmp pin cannot output the expected waveform. To
rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both
the registers immediately after INTTMmn is generated from the master channel (This
applies also to TDRmq of the slave channel 2).
Real-time PER0:
When using the real-time counter, first set RTCEN to 1, while oscillation of the
p.348 _†
counter Peripheral
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the real-
enable register 0 time counter is ignored, and, even if the register is read, only the default value is read.
Clock supply to peripheral functions except the real-time counter can be stopped in p.348 _†
the HALT mode when operating on the subsystem clock by setting RTCLPC of the
operation speed mode control register (OSMC) to 1. In this case, set RTCEN to 1
and bits 0 to 6 of PER0 to 0.
RTCC0: Real- _{If RCLOE0 and RCLOE1 are changed when RTCE = 1, the last waveform of the}
p.349 _†
time counter
32.768 kHz and 1 Hz output signals may become short.
control register 0
R01UH0004EJ0501 Rev.5.01
969
Jun 20, 2011